module 4wayLRUtest;

reg access; // Inputs to state machine
reg [3:0] line;
reg [5:0] curstate;

wire [5:0] nextstate; //Outputs from state machine
wire [1:0] LRU;
wire data_valid;

4way_LRU test_cache (access, line, curstate, data_valid, nextstate, LRU);

initial //Initial input values
begin
  line [3:0] = 4'b0000;
  access = 1'b0;
  curstate = 6'bxxxxxx;
  
  //Tabulated outputs
  $display("\t\t Time  line[3]  line[2]  line[1]  line[0]   state   LRU"); 
  $monitor("%d\t  %b\t    %b       %b       %b      %b      %b",$time, line[3], line[2], line[1], line[0], nextstate, LRU);
  
end


always //test routine
begin

//Basic template for testing the module
#5 curstate = 6'b<insert current state bits>;  //Set the current state
#5 line = 4'b<insert line bits>; //Set the line being accessed
#5 access = 1'b1; //Assert access, then set it back to 0 for next time
#5 access = 1'b0;


$finish;  //end of test routine
end

endmodule
